Array:
We have chosen to use a 2048x2048 HgCdTe "HAWAII-2" array from the Rockwell Science Center. We have chosen this array over the higher quantum efficiency InSb ALADDIN arrays from Santa Barbara Research for several reasons:
· The 2048x2048 format is not
available in InSb material
· The HgCdTe arrays function with low dark currents (<<0.1e-
sec-1) at 77K and can thus be cooled with LN2.
· The HgCdTe arrays provide low read noise (<10 e- with
multiple readouts) and have adequate well depth (10^5 e-) to provide
high dynamic range and background limited spectroscopic performance.
Controller:
The array controller for FLAMINGOS will be a copy of what is now becoming the standard UF array controller. This controller is based on the heritage of the current OSCIR controller (MCE-3 controller) it will be used in the Gemini Mid-IR Imager, a Sofia Instrument called ARIES and FLAMINGOS. All three of these controllers are being built in parallel and the bulk of the design work and prototyping costs are being divided between the three projects. Custom analog electronics, clock drivers and preamplifiers will be build at UF for FLAMINGOS. The hardware associated with the Array Signal Processor (ASP), consists of four major components; the Array Driver board, the Processor board, the ADC board(s) and the Fiber Interface board. These boards reside in a custom VME chassis located in the ASP rack. For the UF FLAMINGOS the ASP rack will transmit data to and from a Linux based PC using a 1 gigabit per second fiber link. We have carried out an analysis of overall noise and dynamic range requirements for the controller based on the expected performance of the 2048x2048 HgCdTe arrays and it appears that all our performance goals can be achieved.
The hardware associated with the ASP, consists of four major components; the Array Driver board, the Processor board, the ADC board(s) and the Fiber Interface board. These boards reside in a custom VME chassis located in the ASP rack. The chassis is a standard 9U, with custom backplanes on J2 & j3. These board are based on a current stable design with ~ 8-12 units in the field. This group of boards are marketed as a set of standard components of array drive electronics available through either the University of Florida or GATIR.
ASP Design:
The ASP that we propose to use for FLAMINGOS is designed to be modular in nature. The main components are designed around the VME 32 specification with a 9U physical form factor. However the remainder of J2 and all of J3 are internally defined. The ASP performs three basic functions; they are to clock the array, digitize and collect the data, and transport the data to a host system. To accomplish these tasks there are three boards that are unique to this system. They are the Pattern Generator board, the ADC/Coadder board(s) and the Fiber board. In addition, there resides in the crate an off the shelf 68XXX processor board which coordinates the activities of the above boards.
Array Clock Generation:
The clocks are generated on the Pattern Generator board. The main components are an address generator and a RAM bank. The array clock lines are taken from the data outputs of that RAM as it is clocked by the address generator. A block diagram of the main functions of the pattern generator board is shown below.
The clocks that the array sees are the output data from the 512K
deep by 32-bit wide Pattern RAM. This RAM is controlled and clocked
by a XILINX Field Programmable Gate Array (FPGA). The FPGA contains
principally an address counter and a pointer which contains the
start address for the counter. It is the function of the higher
levels of the software to determine which area of the clocking
RAM to use and load the address associated with that area into
the Address Pointer register. When the RAM concludes clocking
in the current position the counter will jump to the new location
loaded in that register. Before the clock generator can function,
the RAM must be loaded with the appropriate data values. These
values are calculated at system bootup and loaded over the VME
bus through the data switch. Once complete, the switch is toggled
to the operate position and normal clocking will commence on command.
The higher level software is signaled with an interrupt over the
VME bus that a pattern sequence has begun. This causes the software
to fetch the new sequence address. The only requirement on system
timing is that the software return the next desired address before
the current sequence is completed. Normally for arrays of the
size considered for FLAMINGOS, the sequence is the entire length
needed to clock the array fully one time. A typical frame time
of 3 ms is more than adequate for the system IRQ handler. The
only limit to the length of the sequence is the amount of memory
available.
Clocking Modes:
It may be desirable to have more than one mode to clock an array. Several examples are:
1) Destructive read
2) Non-destructive read
3) Idle
The standard scenario is for the array to be clocked all the time
to ensure a stable detector temperature. At power-up the idle
mode is initiated. Then, when acquiring data, the array is run
in the destructive read mode. Once the observation is completed,
the array is returned to the idle mode.
Coadder Section:
The coadders are implemented using Xilinx FPGAs. The incoming
ADC data is then accumulated in the coadder RAM buffers. This
accumulated data is transferred to the on-board data buffer when
a predetermined number of frames have been coadded. Each accumulator
RAM is divided into four different areas (A through D for this
discussion). However only two of the accumulator buffer areas
are normally used.
The purpose of the on-board buffer is to decouple the backplane and fiber data rates from the raw frame data rates. Without this buffer the backplane has to take the full bandwidth of the array data at peak pixel rates. While this is just a bit too high for both the backplane and the fiber link, it may be substantially higher than the host system can absorb. However, with the on-board data buffer, the only operational constraint is that the buffer be read out completely before the next image is completed.
Back plane:
In a previous version of this architecture,
the data transfer rates across the backplane became a central
issue. In that design, there was no on-board buffer so that the
backplane had to keep up with the raw data rates. Also, the backplane
data path was 32-bits wide. With the change to 128-bits an automatic
factor of four is gained in throughput. While incremental gains
could be achieved by carefully optimizing the design timing and
increasing the clock speeds, it was decided that a slower overall
clock speed and a lower risk approach to the throughput problem
was preferred. With a 10 MHz clock, the burst rate across the
backplane is 160 Mbytes / sec. The average sustained rate, with
very conservative timing is 95-100 Mbytes / sec. This is a good
match to the peak rates that the fiber link can absorb.
Fiber Link data rates:
The Giga-bit fiber optic link uses the
Vitesse series of fiber channel chips to encode and decode the
fiber data. This link handles both the array data being transferred
to the host as well as the command and control channel. The peak
data rate that the fiber will support is 106 Mbytes / sec. The
fiber board is a custom board by EDT.
Summary:
The two major changes from the system
that has been in use here at the University of Florida, are the
addition of a data buffer on each ADC board and the increasing
of the effective bandwidth of the backplane. These changes allow
our system to operate at the ADC maximum conversion rates (2 MHz,
much more than the 300-500KHz rates of the HgCdTe arrays) while
still running the remainder of the data chain in a conservative
manner and still retaining the high resolution afforded by the
use of 16-bit converters.